LSA101 Laser Spike Anneal System

Utilized by leading IDMs and foundries around the globe, Ultratech’s LSA101 system is utilized as the preferred technology for high-volume manufacturing of advanced logic devices from the 40nm to 14nm nodes. Built on the customizable Unity Platform™, the LSA’s scanning system has fundamental advantages in uniformity and low-stress processing, which make it readily applicable for current and future device nodes. The LSA101 enables critical millisecond annealing applications that allow customers to maintain high processing temperatures, and thus achieve improved device performance, lower leakage, and higher yield.

The standard LSA101 configuration utilizes a single narrow laser beam to heat the wafer surface from substrate temperature to the peak annealing temperature. An LSA dual beam technology was developed to expand the application space of non-melt laser annealing and features a second low-power laser beam to enable low-temperature processing.  When using dual beam a second wider laser beam is incorporated to preheat the wafer. The dual beam system offers flexibility in tuning the temperature and stress profiles.

LSA201 Ambient Control Laser Spike Anneal System

Ultratech’s LSA201 Laser Spike Annealing system has the same architecture as the LSA101 but includes a patented micro chamber design which enables full-wafer ambient control in a scanning laser system. The micro chamber is unique in that it does not require the use of a vacuum load-lock. The system is capable of running mixtures of any inert gases including forming gas. The LSA201 targets applications such as high k metal gate junction activation and nickel silicide formation. The LSA201 is well suited for processes at sub-20nm, such as interface engineering and material modification where ambient control is critical. 

Key Features

  • Long wavelength, Brewster angle, p-polarized light for optimum within-die uniformity
  • Closed-loop temperature feedback control to maintain tight temperature control
  • Layout independent design ideal for processing both planer and FinFET devices
  • Localized stress field with flexible dwell time enables low stress processing and reduced wafer breakage